Power semiconductors, widely used as switches, feature low on-resistance, high blocking voltage, and effective heat dissipation, enabled by copper metallizations. However, excessive thermomechanical stresses and ultrafast heating rates (~10⁶ K/s) significantly impact metallization lifetime. This degradation is driven by localized deformation modes, high-temperature pulses, and stress accumulation. Predicting these effects through modelling could save substantial time and costs. Previous studies revealed that time-independent thermo-mechanics and plasticity are insufficient. Instead, creep processes must be included, as they predict pore growth, a degradation indicator, when tensile stresses and high temperatures co-occur. Additional mechanisms like dislocation pile-up or grain boundary sliding are required to explain tensile stress hotspots, necessitating a microstructure-sensitive, multi-mechanism modelling approach. Degradation of copper metallization under extreme short-circuit pulses was investigated using chip test structures (polyheaters), which facilitate in-situ measurements such as electrical resistance monitoring [2] and time-resolved synchrotron experiments [3]. These studies revealed that stress levels during short pulses (heating rates up to 10⁶ K/s) significantly exceed those in conventional experiments (<1 K/s). Thermodynamically induced vacancy supersaturation was identified as the initiating damage mechanism. A simplified creep law applied to grain boundaries in a 3D microstructural finite element model captured local tensile hotspots. Classical creep theory accurately predicted pore growth rates, aligning with experimental observations. A sub-model approach resolving critical microstructural regions within a larger thermo-mechanical chip model demonstrated the relationship between short-circuit pulse parameters and microstructural creep behavior. This approach provides insight into the lifetime variation of metallizations and informs the development of improved technologies.